The present invention is directed to semiconductor devices, and more particularly to a clock circuit for semiconductor memory devices.
FIG. 1 shows an exemplary memory interface in a low-power synchronous dynamic random access memory (SDRAM) device. A data bus (DQ bus) 10 is interfaced between an LP-DDR memory chip 20 and a controller 30. The controller 30 generates a memory clock (MemCLK) signal that is connected to the CLK input of the memory chip 20. In low-power semiconductor devices, such as low power-single data rate (LP-SDR) or low power-double data rate (LP-DDR) SDRAM devices, the read access to load valid data onto the data bus 10 is triggered by clock edges of the MemCLK signal.
Turning to FIGS. 2(A) and 2(B), there is a read access time (tAC) that results from an intrinsic delay path as shown with respect to the main clock signal (CLK). It is very difficult to significantly improve tAC. The controller 30 can sample and resynchronize the data stream if tAC is short enough so as to allow for sufficient set-up time. However, as clock signal frequencies become faster with improving semiconductor technologies, the clock cycle time (tCK) will become so small that tAC may exceed tCK.
By contrast, commodity DDR SDRAMs for applications that are not power sensitive use delay lock loop (DLL) circuits to align data bus (DQ) access to a clock edge. As shown in FIG. 3, DQ switching is aligned to clock edges so that tAC approaches 0 ns, so-called “edge-aligned”. Again, this is possible because an on-chip DLL circuit generates early clock cycles that align the data output to clock edges. A DLL circuit may consume a few milliamps (mA) even when the host device is in stand-by mode if the clock is running. A DLL circuit is rarely used in semiconductor devices for low power applications because the DLL power consumption even in a stand-by mode may quickly deplete the battery of the system.
The present invention provides a circuit technique to generate a delayed clock signal to drive read output thereby ensuring that the read access time tAC does not exceed the clock cycle time tCK.